(1) Field of the Invention
The present invention relates to a transmission device and an integrated circuit, and more particularly, to a transmission device for controlling transmission of digital signals and an integrated circuit having a signal rate conversion function built therein and packaged on a semiconductor substrate.
(2) Description of the Related Art
With the recent advance of computer technology and optical fiber technology, synchronous multiplexed networks that provide advanced communication services, such as high-speed computer communications and multimedia communications, have come to be widely used.
Multiplexing techniques used in constructing synchronous multiplexed networks include SDH/SONET transmission system as a core technique. SDH/SONET, which prescribes an interface for effectively multiplexing various high-speed services or existing low-speed services, has been standardized and is still being developed.
Meanwhile, transmission systems of this type are required to have a large-scale multiplexing capability because of an increasing capacity of channels to be handled, and thus their functions are divided into a plurality of LSIs. Such LSIs, which are arranged in multiple stages according to their function, perform P/S (Parallel/Serial) conversion at individual output stages and process signals with the interface speed gradually increased.
FIG. 10 shows the configuration of a conventional P/S LSI. The P/S LSI 20 comprises a PLL (Phase Locked Loop) section 21 and a P/S section 22. The PLL section 21 is constituted by a phase comparator 21a, a PLL 21b including a VCXO (voltage controlled crystal oscillator) 21b-1, and a frequency divider 21c. 
A clock driver 30 outputs a clock signal ck1, and an LSI 40 outputs n-parallel data D1 which has been processed using a delayed clock signal ck1.
The PLL section 21, which uses the clock signal ck1 as a reference clock signal, constantly performs feedback control on a clock signal ck1b, of which the frequency is 1/n of that of a clock signal ck2 output by the PLL section 21, with reference to the clock signal ck1 so that the clock signal ck1b may keep time with the clock signal ck1.
The phase comparator 21a compares the phases of frequencies of the clock signals ck1 and ck2 with each other and outputs a phase difference. The PLL 21b converts the phase difference to a direct-current voltage and outputs the resulting voltage to the VCXO 21b-1 provided therein, and the VCXO 21b-1 generates an output frequency proportional to the direct-current voltage. The frequency divider 21c supplies the phase comparator 21a with a frequency-divided signal (clock signal ck1b=clock signal ck2/n) obtained by dividing the frequency of the clock signal ck2 by n. Thus, in the PLL section 21, the VCXO 21b-1 is controlled so that the frequency-divided signal may be in phase with the clock signal ck1.
The P/S section 22 uses the clock signal ck1b as a write clock signal to write the low-speed n-parallel data D1, and uses the clock signal ck2 as a read clock signal to serially read out the written data, thereby outputting serial data D2 at an increased interface speed.
In the P/S LSI 20 described above, it is necessary that the phase relation between the low-speed clock signal ck1 and the clock signal ck2 output by the PLL section 21 should be determined beforehand, in order to reduce a steady-state phase error, and also that the low-speed data D1 should be input in accordance with the predetermined phase relation.
Accordingly, at the stage of design, the output phase of the LSI 40 must be matched with the fetch phase of the P/S LSI 20, or an additional component must be mounted to the unit for the purpose of adjustment. This makes the circuit configuration specific to the unit used, so that the flexibility is lost and also that a heavy burden is imposed on design and development.
On the other hand, P/S LSI products have recently come to be available which include a FIFO (First-In, First-Out) circuit for the purpose of relaxing the regulations on phases. FIG. 11 shows the configuration of a conventional P/S LSI including a FIFO circuit.
The P/S LSI 20a includes a FIFO circuit 210, in addition to the aforementioned PLL section 21 and P/S section 22. The FIFO circuit 210 comprises an elastic store memory 211, a write counter 212, a read counter 213, and a phase monitoring section 214.
A clock driver 30 outputs a clock signal ck1, and an LSI 40 outputs n-parallel data D1 processed using the clock signal ck1, as well as a clock signal ck1a obtained by delaying the clock signal ck1.
Based on the clock signal ck1a, the write counter 212 generates a write address for writing the data D1 in the elastic store memory 211. Based on the clock signal ck1b, the read counter 213 generates a read address for reading out the data D1 written in the elastic store memory 211.
The elastic store memory 211 has a depth of m (m memory stages) and, in response to the clock signal ck1a, writes the data D1 in the corresponding write address. Also, in response to the clock signal ck1b from the PLL section 21, the elastic store memory reads out the data D1 from the read address.
Using the clock signal ck1b, the phase monitoring section 214 monitors the phases of the write and read addresses. If the write and read addresses are in such a phase relation that the write and read operations cannot be normally performed, the phase monitoring section sends a reset signal SET to the write and read counters 212 and 213, to reset the phase relation.
The P/S section 22 uses the clock signal ck1b from the PLL section 21 as a write clock signal to write the n-parallel data D1 output from the FIFO circuit 210, and uses the clock signal ck2 as a read clock signal to serially read out the written data, thereby outputting serial data D2.
With the P/S LSI 20a including the FIFO circuit 210, the regulations on the fetch phase of low-speed data can be relaxed. Accordingly, the use of such flexible LSI makes it unnecessary to establish regulations on the phases within the device at an initial stage of development, and also lightens the burden on design and development.
However, the conventional P/S LSI 20a described above is constructed such that the resetting is carried out only when the values of the write and read addresses are in exact coincidence. Thus, while the values of the write and read addresses are very close to each other and about to coincide, the operation is judged to be in a normal state and no resetting Is performed, giving rise to a problem that the operation is continued in an unstable state.
FIG. 12 is a time chart showing the resetting operation performed by the P/S LSI 20a, wherein it is assumed that the number n of parallel data is xe2x80x9c4xe2x80x9d (n=4) and that the depth m of the elastic store memory 211 is xe2x80x9c7xe2x80x9d (m=7). Data is written in the write address WA at the leading edge of each clock pulse ck1a, and data is read out from the read address RA at the leading edge of each clock pulse ck1b. The resetting is performed when the reset signal SET turns to xe2x80x9cHxe2x80x9d, and upon resetting, the phases of the write and read addresses are reset to be in an optimum phase relation.
First, at the startup, the values of the write and read addresses WA and RA are set at optimum positions (WA=1, RA=4) by the reset signal SET.
If the clock signal ck1a is perturbed due to an external factor, such as ESD (electrostatic discharge), within an interval A and the values of WA and RA become coincident with each other, the WA and RA values are reset to their original optimum positions by the reset signal SET (in this case, although a read error occurs in the elastic store memory 211, it is not treated as a target of normal evaluation because the erroneous operation was caused by an external factor, such as ESD, which is outside the coverage of guarantee).
FIG. 13 is a time chart illustrating a problematic operation of the P/S LSI 20a. At the startup, the values of the write and read addresses WA and RA for the elastic store memory 211 are set at optimum positions (WA=1, RA=4) by the reset signal SET, as in the case of FIG. 12.
Let it be assumed that in an interval B, the clock signal ck1a is perturbed due to an external factor such as ESD, causing the phase relation to change to an extent such that the values of WA and RA are very close to each other and about to coincide. In such a situation, no resetting is performed, so that the operation is continued in an unstable state near slip.
While the operation is thus continued in an unstable state, the phase relation between the clock signals ck1a and ck1b can possibly be changed (in the illustrated example, the clock signal ck1a is displaced backward with respect to the clock signal ck1b) due to factors such as fluctuations in temperature or power supply (these factors are very probable even in normal operating conditions and the operation needs to maintain normality within the coverage of guarantee) such that the values of WA and RA exactly coincide with each other. If this occurs, the resetting takes place even though the device is operating in normal operating conditions.
Thus, with the conventional P/S LSI 20a, if the operation shifts to an unstable state due to an external factor such as ESD which is outside the coverage of guarantee, without the resetting being performed, and if the operation in such an unstable state undergoes a further change due to a factor such as fluctuations in temperature or power supply, the resetting takes place even though the device is operating in normal operating conditions, thus lowering the quality and reliability of the device.
The present invention was created in view of the above circumstances, and an object thereof is to provide a transmission device which is improved in the quality and reliability of digital transmission control.
Another object of the present invention is to provide an integrated circuit which is improved in the quality and reliability of digital transmission control.
To achieve the first object, there is provided a transmission device for controlling transmission of digital signals. The transmission device comprises a memory for storing an input signal, write address generating means for generating a write address for writing in the memory, read address generating means for generating a read address for reading from the memory, phase state monitoring means for monitoring a transition from a steady phase state in which writing/reading in/from the memory is normally performed or from a startup state to a coincident phase state in which address values of the write and read addresses coincide with each other or to an unstable phase state in which a phase fluctuation margin is one-sided, and reset signal output means, responsive to detection of the coincident phase state or the unstable phase state, for outputting a reset signal to the write address generating means and the read address generating means such that a phase relation between the write and read addresses is brought to an optimum phase relation.
Also, to achieve the second object, there is provided an integrated circuit having a signal rate conversion function built therein and packaged on a semiconductor substrate. The integrated circuit comprises a PLL circuit for generating an output clock signal by multiplying an input clock signal, which is synchronized with an n-parallel signal, by n while keeping time with the input clock signal, a FIFO circuit including a memory for storing the parallel signal, write address generating means for generating a write address for writing in the memory, read address generating means for generating a read address for reading from the memory, phase state monitoring means for monitoring a transition from a steady phase state in which writing/reading in/from the memory is normally performed or from a startup state to a coincident phase state in which address values of the write and read addresses coincide with each other or to an unstable phase state in which a phase fluctuation margin is one-sided, and reset signal output means, responsive to detection of the coincident phase state or the unstable phase state, for outputting a reset signal to the write address generating means and the read address generating means such that a phase relation between the write and read addresses is brought to an optimum phase relation, and a P/S circuit for converting the parallel signal read out from the memory to a serial signal in response to the output clock signal.